According to Inha University professor Rino Choi
The semiconductor industry has focused on reducing the size of the chip so far. But microfabrication today is nearing its limits. Technology competition between semiconductor companies are now moving to packaging, which is moving away from traditional wire bonding and soldering to multi-function, very large scale integration using new advanced packaging technologies.
Heterogeneous integration, which allows for multiple functions to be integrated into one chip, is getting the spotlight. New names for new packaging methods such as fan-out, interposer, hybrid bonding, Foveros, and others, are thrown around daily.
Semiconductor powerhouses TSMC, Intel and Samsung, which has previously focused more on the front-end process of semiconductor production, has begun to focus on back-end, or packaging, process technologies. The governments in the US and Japan are also showing support for packaging technology development. South Korea is also giving out national projects on packaging technology.
TheElec’s JY Han met with Rino Choi, professor of new materials science and engineering at Inha University, to talk about heterogeneous integration technology and the recent trends in the semiconductor packaging space. The following interview has been edited for clarity and brevity:
Q: Earlier this year, TSMC said it has not come up with a roadmap after 2-nanometer (nm) and mentioned packaging. AMD also recently mentioned a new packaging technology. Packaging is also called the back-end process.
A: Yes. It is called the back-end process.
Q: There is a front-end and a back-end. In the past, those working in the front-end space use to say, “back-end is not advanced technology”. It seems this has changed in recent years?
A: The perception has changed a great deal in recent years. TSMC, through its technology called Integrated Fan-Out, received all the orders from Apple. It made quiet a profit through this back-end process technology. The deal showed that back-end process technology could be the key technology. Since then, back-end process has become an important focus for semiconductor companies.
*Editor’s note: Fan-out doesn’t use a printed circuit board and instead connects the I/O terminals of the chip and those on the chip’s outer surface. This offers more integration and improved electrical performance. In 2016, TSMC developed Apple’s application processor and DRAM memory using fan-out, which it calls Integrated Fan-Out, or InFO. Fan-out market has grown substantially since then.
Q: InFO is called fan-out in general in the industry.
A: Yes. Samsung is also developing its own fan-out technology.
Q: Prior to that, it was panel level package.
A: Yes, Samsung does panel level package (PLP) and wafer level package (WLP).
Q: Put simply, some of the packages are square shaped (panel) and others are circular (wafer). Packaging methods have changed a lot over the years. Isn’t spending required in packaging less compared to front-end processes?
A: Yes. Today, building a high tech fab requires around 10 trillion won in funding. By comparison, spending in packaging is very small. For the front-end process, equipment for extreme ultraviolet (EUV) and those to reduce gate width are required, which increases CAPEX substantially.
Q: TSMC says it has now roadmap after 2-nm. Is there now solution for more integration?
A: Gate all around (GAAFET) has been commercialized. Samsung is developing 3-nm.
*Editor’s note: Unlike FinFET, which uses three surfaces for the gates (top, left and right), GAA also uses the bottom surface, and is sometimes called 4D. GAA increases integration and allows for the making of extremely small transistors.
There are talks of complementary FET, vertical FET and other technologies, but no companies has developed a device using these technologies. There are many obstacles these technologies to be applied. It will also require a lot of spending, so it is going to be a tough road ahead for semiconductor companies.
*Editors note: Complementary FET is being touted as possible to realize 1-nm. Two different kinds of FET are made on one silicon, which reduces the surface and cost. Vertical FET uses an epitaxial substrate and puts the drain electrode on the bottom layer and the sources electrode on the top layer. The gate electrode are put inside the epitaxial middle layer. The structure is usually used in power devices.
Q: 7-nm and 5-nm are currently in production. Lets say 3-nm and 2-nm goes into production down the road, but there is no next processes afterwards. Will the chip industry stay at 3-nm and 2nm?
A: Unlikely. In whatever format, there will be a demand for higher performance from chips. Semiconductor scaled [their integration] to increase chip performance. They used these technologies to make chips, sell it to customers, and used the money from their customers to reinvest to scale further. This has been the way for semiconductor transistors. This has been what is called “Moore’s Law”.
But this is changing. Scaling no longer solves all problems. Scaling is also becoming more difficult and more expensive. That is why TSMC began pushing packaging.
Q: So shall we call that “More than Moore” or “Beyond Moore”?
A: “More than Moore” is quiet an apt description. “Beyond Moore” is a different concept. “More than Moore” means combing logic and memory chips. This could mean a combination of MEMS and sensor. There is a need for all these different functionalities to be integrated into one chip because mobile form factors are becoming smaller. This is where heterogeneous integration comes in.
Editor’s note: Heterogeneous integration uses processes such as redistribution layer (RDL) instead of the previous soldering and wire bonding to integrate various devices such as processors, memory, sensor, RF and MEMS.
Q: Could you share the details on what AMD announced recently at Computex Taipei?
A: AMD introduced a technology called V-Cache with its Gen 3 Ryzen CPU. This technology puts the SRAM atop the CPU. Previously, it was conventional to use a micro bump to attach the RAM on the CPU and make them into one chip. In contract, V-Cache uses direct copper-to-copper bond to make them into one chip without a bump.
Q: The technology has been touted as revolutionary by experts in the field.
A: It is a great example of heterogeneous integration done well. Heterogeneous integration got the spotlight around the time ITRS said it won’t make the roadmap for semiconductor development in 2015. This was because microfabrication was becoming difficult in the front-end and there wasn’t many customers that needed such advanced roadmap.
Instead, they begin making the heterogeneous integration roadmap, or HIR. HIR means there needs to be a lot of joint effort to develop technology at the system at the level to stack various chips into one.
Heterogeneous is different from homogeneous. There are many factors such as logic, memory and function, but the most important is technology node. There are chips that require expensive 3-nm and 5-nm nodes, while others can be made using 22-nm. This means making chips into one chip isn’t always advantageous in terms of yield rate and supply chain. Chips that need to made small are made small; those that need high performance are made as such; those that require neither are made they way they are made; all of these are combined at the system level. This is heterogeneous integration.
*Editor’s note: HIR was drawn by the Electronics Packaging Society of the IEEE.
Q: For previous SoCs, the GPU, the CPU and memory cache were made in one die.
A: Now they are trying to do this at the packaging level. There are many technologies for this: Fan-out, interposer and hybrid bonding. The important thing is that here needs to be a lot of I/O when the chips are bonded together.
Q: They need to transmit data back and forth.
A: Precisely. Making various devices into one chip only makes sense if there are great number of I/Os. I/O reduces delay and power consumption. Stacking is the way to shorten them. Micro bump limits the number of I/O. When a chip is made, then bonded, this can cause the product to be too thick. This makes alignment difficult. The bump needs to be made bigger and this limits the number of I/O further.
Q: This is where fan-out comes in.
A: Yes. I/O number was increased by expanding the area. But now they are bonded through copper-to-copper. Copper is used to make the interconnect metal. The back-end is also made with copper. These are then cut and bonded. Ideally, there can a great number of I/O.
Q: It will also be faster.
A: Yes, it will offer faster speed.
Q: If copper and copper are bonded, balls are no longer required right?
Q: Intel offers Foveros. Doesn’t this technology use bumps?
A: It uses micro bumps.
*Editor’s note: Foveros, instead of placing the computer tiles next to each other, they are stacked vertically. It is a logic-on-logic structure that allows for 3D stacking even in high performance processors.
Q: AMD is using TSMC for copper-to-copper. Lets say this becomes the main trend. Companies that put in the underfill for the bumps could see their material use drop substantially, couldn’t they?
A: Not all products can go copper-to-copper. It will be an expensive process, so it will be applied to markets where it is needed. Any chips that require a great number of I/O will be premium. This copper-to-copper sector will grow however.
Q: First it was wire bonding, then ball, now direct bonding. Will wire bonding become a technology of the past? What about bump?
A: Wire bonding is still used in various sectors. It won’t go away. Bump will also be a cheaper process. There are product categories that will require the process.
Q: The market will value a company with a future technology instead of past technologies. In South Korea, how is the research and development into heterogeneous integration going?
A: So far, this particular technology hasn’t been given out as a national project. In the Biden Administration’s 100-day supply chain plan, advanced packaging is mentioned. It also says the National Semiconductor Technology Center will be providing the funding.
Q: So the US government is directly involved?
A: The US prefers to have individual companies do the research, while the country fosters talent and provides the infrastructure. The new policy means their national agenda is changing. They left the private sector to develop technologies in the area; now it is done all in foreign countries. So I think there was a voice for packaging technology to be developed at the government level. This includes advanced packaging.
Q: TSMC and Japan are collaborating in packaging.
A: Japan has a great research infrastructure for packaging. It has researched the field for a long time. TSMC is considering packaging very important.
Q: There are also outsourced semiconductor assembly and testing firms. Do these companies now require heterogeneous integration technologies?
A: They will need a lot of related technologies. TSMC is growing fast based on such technologies. The next step will be to make passive devices at the chip level. This will require capacitor and registry, which will in turn require a great front-end competence. This could be wafer-to-wafer, die-to-wafer, or die-to-die. They could look for known good dies and bond them with known good dies.
Q: You participated in IEDM many times. Is that the recent trend?
A: Yes. Front-end has reached its limit. Interuniversity Microelectronics Center do research in simulation for complementary FET and vertical FET. But those in the front-end are more interested in stacking. My research area is also in monolithic 3D. There are many discussions on how to bond or stack devices at the packaging level.