Kioxia and Western Digital announced that they have developed their Gen 6 162-layer 3D flash memory.
The latest chip, thanks to a new architecture beyond the conventional eight-stagger memory hole array, has up to 10% greater lateral cell array density compared to the Gen 5, the pair said.
The new flash memory also has 40% reduced die size compared to 112-layer version and more optimized cost, the companies said.
They also applied Circuit Under Array CMOS placement and four-plane operation, which together deliver nearly 2.4 times improvement in program performance and 10% improvement in read latency compared to Gen 5, Kioxia and Western Digital said, while I/O performance also improved by 66%.
Cost per bit reduced and manufactured bits per wafer is increased by 70% compared to the previous generation, they said.
