UPDATED. 2024-06-25 16:02 (화)
How will EUV tech in wafer fabrication evolve?
How will EUV tech in wafer fabrication evolve?
  • Jang Keyoung Yoon
  • 승인 2022.01.06 16:09
  • 댓글 0
이 기사를 공유합니다

Experts at Hanyang University EUV-IUCC give the lowdown on related technologies
Image: TheElec
Image: TheElec

Extreme ultraviolet (EUV) lithography is a hot topic in the semiconductor industry right now.

Interest in the technology has steadily risen since Samsung first adopted an EUV equipment for its 7-nanometer (nm) foundry service in 2017.

The need for more advanced chips in 3nm and 2nm nodes, which is fueling the development of more microfabrication technologies, that started last year is increasing the adoption of EUV by major chip makers. Dutch firm ASML, the sole manufacturer of EUV equipment, can’t manufacture enough of them from the high demand __ Samsung, SK Hynix, TSMC and Intel are all lining up to procure them.

EUV, first applied in logic chips, is now being used in memory production __ specifically in DRAM. Samsung applied EUV for the production of its 10nm DDR4 DRAM for the first time in 2020, while SK Hynix followed suit the following year.

But EUV technology is far from complete. It is just beginning. Experts at Hanyang University’s EUV Industry-University Collaboration Center (EUV-IUCC) tell TheElec that associated technologies are also still evolving. We take a look at some of these areas that will affect EUV ecosystem's progress going forward.

1. Multiple patterning

Multiple patterning technology for DRAM will likely be applied starting in 2030 at the earliest, according to Hanyang Unviversity professor Oh Hye-keun. “We must make a distinction between memory and logic semiconductors when it comes to how fine a circuit can be drawn using EUV,” Oh said. “When foundry companies like TSMC talk about 3nm node, they are talking about application specific integrated circuit (ASIC). If we convert this for memory, than it becomes 16nm node.”

“Through EUV, memory device will be able to reach 2nm and 3nm nodes, which is quantum mechanically proven to be viable,” the professor said. “Currently, out of the 30 some layers in semiconductors, EUV is being applied to five layers. But this will increase going forward.”

Given all these developments, multiple patterning technology will be applied in EUV process between 2030 and 2035, the professor predicted. 

2. Atomic Layer Deposition (ALD)

ALD will also be used more in the coming days when it comes to the EUV process. ALD can deposit layers that are 0.1nm thin. ALD’ lacks behind in speed to conventional chemical vapor deposition (CVD), but their application is increasing for advanced chips.

Hanyang University professor Park Jin-seong said: “As foundry companies compete in nodes under 5nm, more of them will adopt ALD. For ultra microfabrication, CVD has limits.”

Major research centers are developing ways to deposit only on selective surfaces, he added.

3. Pellicle

Pellicle is a key commodity used to protect the masks used in the EUV process. EUV masks cost between 500 million won to a billion won a piece, so their protection is key. However, the pellicle themselves are also very expensive, in the tens of millions of won, and are very difficult to clean.

Hanyang University professor Kim Tae-gon said: “Technology is being developed where we can clean the EUV pellicle and remove particles without impacting them physically or chemically. Pellicle are very, very thin: they can crack on their own in an ambient atmosphere. The smallest pressure can also crack them. Currently, equipment that can resolve this issue are in the trial stages.”

Use of these equipment can extend the life of EUV pellicles drastically, which will lead to innovative cost saving for chip companies, Kim explained.

4. Packaging

Development in packaging will also go hand-in-hand with EUV. Microfabrication in the front-end process is reaching their limit, Hanyang University professor Kim Hak-sung noted, so packaging technology that can integrate chips at high density is increasing. Small devices like wearables are also fueling this development, the professor said.

Because of this, major foundry companies are aware of the importance of packaging, Kim said. Out of various packaging technologies, multi-chip packaging will be key, the professor noted. “Because DRAM are now stacked in 3D in eight layers or twelve layers, highly sophisticated technology to organically connect these layers are developing fast,” Kim said. 

However, compared to Taiwanese outsourced assembly and test firms, which developed their technologies with TSMC, South Korea’s related ecosystem was currently less mature, the professor noted. There is a need for related South Korean companies to develop packaging technologies because of this, Kim said.

5. Research infrastructure

South Korea’s infrastructure around EUV research was also lacking, POSTECH professor Lee Sang-sul said. POSTECH was the only research institute with the equipment to research the light characteristics of EUV, Lee said, and this is not enough.

There is research infrastructure around lithography and inspection, but those to develop next-generation processes is very lacking, the professor noted. There needs to be infrastructure, preferably those of a public nature, for a healthy ecosystem around EUV to foster in South Korea, he added.

삭제한 댓글은 다시 복구할 수 없습니다.
그래도 삭제하시겠습니까?
댓글 0
계정을 선택하시면 로그인·계정인증을 통해
댓글을 남기실 수 있습니다.

  • 515, Nonhyeon-ro, Gangnam-gu, Seoul, Republic of Korea 4F, Ahsung Bldg.
  • 대표전화 : 82-2-2658-4707
  • 팩스 : 82-2-2659-4707
  • 청소년보호책임자 : Stan LEE
  • 법인명 : The Elec Inc.
  • 제호 : THE ELEC, Korea Electronics Industry Media
  • 등록번호 : 서울, 아05435
  • 등록일 : 2018-10-15
  • 발행일 : 2018-10-15
  • 발행인 : JY HAN
  • 편집인 : JY HAN
  • THE ELEC, Korea Electronics Industry Media Prohibiting unauthorized duplication,publishing,modification and distribution the material on this Site for any purpose.
  • Copyright © 2024 THE ELEC, Korea Electronics Industry Media. All rights reserved. mail to powerusr@thelec.kr