DRAMs launching in the future may be made with hybrid bonding applied, a TechInsights analyst said on Thursday.
This is because it will allow chipmakers to increase the density of the DRAM to increase their capacity, analyst Jeongdong Choe said during a seminar hosted by SEMI in Suwon, south of Seoul.
LPDDR5X and other latest memory chips only had a cell array efficiency of 50% at the current stage, Choe said.
If like NAND, chipmakers can make the DRAM array die and make the peripheral separately, this could maximize density, he said.
Peripheral handles logic work in a DRAM. Current DRAM includes the logic circuits inside it. Choe is proposing that this be separated so that the space can be used to pack in more memory circuits.
NAND chips already have the peripheral underneath the memory cell to increase their densities.
Hybrid bonding refers to the bonding of a heterogeneous die and the wafer allowing improvements in I/O and circuit lengths.
Samsung, SK Hynix, and Intel are preparing to apply the process in their chip-making, according to analysts.
Choe said in China, products that have the CMOS logic and DRAM die hybrid bonded have already been produced and launched in the market.
Samsung and SK Hynix could make 32Gb DRAM using this same method, he said.
Meanwhile, the analyst also said that 3D DRAM is difficult to develop as unlike gate-all-around NAND __ a 3D NAND __ DRAM faces homogeneity issues if made in 3D
That is why memory chip makers will likely develop 4F square instead for the upgrade.
Samsung is developing 4F square memory chips while SK Hynix and Micron are focusing on 3D DRAM. 4F square is a cell array structure that is an upgrade from 6F square and can reduce the surface area of the die by 30%, according to analysts.
