UPDATED. 2024-06-20 07:03 (목)
Samsung to develop a 16-stack 3D DRAM
Samsung to develop a 16-stack 3D DRAM
  • Noh Tae Min 기자
  • 승인 2024.05.20 19:58
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Double that of Micron’s 8-stack
Image: Applied Materials
Image: Applied Materials

Samsung is developing a 16-stack 3D DRAM, a senior company executive said.

Siwoo Lee, executive vice president of DRAM pathfinding at Samsung, told reporters during the International Memory Week event lat week that some companies, including Samsung, are preparing samples for a 16-stack 3D DRAM. Micron is known to be developing an 8-stack model.

However, the executive added that Samsung was looking at the feasibility of 3D DRAM, or vertically stacked cell array transistors (VS-CAT), at the current stage rather than preparing for mass production. Lee joined Samsung last year and handled research into future memory chips at Micron previously.

VS-CAT, unlike existing DRAMs, combines two silicon wafers. The peripheral, or logic, and memory cells are attached individually. YMTC’s Xstacking technology shares a similar concept.

For 3D DRAM, attaching the peripheral next to the cell layer like existing DRAMs will cause it to have too large a surface area.

That is why the peripheral is made on another wafer to the memory cells and attached through bonding.

3D DRAM is expected to be made through hybrid bonding technology such as wafer-to-wafer, which is already being applied to NAND and CMOS image sensor production.

Meanwhile, Samsung also mentioned that it could apply backside power delivery network (BSPDN) technology to 3D DRAM. 

 


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