UPDATED. 2024-06-20 07:03 (목)
SK Hynix to apply PCU tech for PRAM
SK Hynix to apply PCU tech for PRAM
  • Nari Lee
  • 승인 2021.02.03 20:00
  • 댓글 0
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Chip combines benefits of NAND flash and DRAM
Image: SK Hynix
Image: SK Hynix

SK Hynix will apply peri under cell (PUC) technology to its next-generation phase-change RAM (PRAM), the company said on Wednesday.

PRAM combines the advantages of DRAM and NAND flash. Intel retained its Optane business, which is based on PRAM technology, when it sold its NAND unit to SK Hynix. PRAM is considered a key technology for the data center business.

SK Hynix team leader Lee Hyung-dong said at Semicon Korea 2021 that the company has applied PUC and a designated algorithm to its PRAM that meets the requirements for it to be classed as storage class memory in performance and costs.

The company’s PRAM technology has increased in competence in terms of cost, density and memory capacity as a result, Lee said. The PRAM can be used in data centers and neuromorphic computing.

PUC puts the peripheral circuits on the cell beneath the cell to reduce chip size and increase productivity. Lee said PRAM has less limitations in scaling compared to memories under 10nm. It is also amorphous, making it easy to be stacked in 3D.

SK Hynix also applied its double stack technology to the PRAM. The technology holes the memory twice. Being doubly stacked allows the cell to take up less space while increasing its reading and writing speeds. SK Hynix expects PRAM to have 4 stack and 6 stack technologies applied later on.

Applying stacking technology on PRAM had advantages in bit growth, cost saving and performance increase, Lee said. PRAM will contribute in improving system performance in the age of data-centric computing, he added.

PRAM responds faster than NAND flash while unlike DRAM, it is non-volatile. It uses materials that changes from amorphous to crystalline depending on the amount of electricity. The downside is that it is more prone to interruption from overheating.

SK Hynix began development of PRAM with IBM back in 2012. It published its development of a 128GB PRAM that uses 3D crosspoint structure at IEDM in 2018.

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