UPDATED. 2023-01-27 13:47 (금)
Samsung to use BSPDN tech for 2nm chip
Samsung to use BSPDN tech for 2nm chip
  • Kang sung tae
  • 승인 2022.10.13 17:19
  • 댓글 0
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Tech upgrade to chiplet design used by Intel
Image: IMEC
Image: IMEC

Samsung is planning to use a technology called back side power delivery network (BSPDN) to develop 2-nanometer (2nm) foundry process.

The technology was introduced last week at SEDEX 2022 hosted by Samsung by researcher Park Byung-jae.

Park had said in the foundry market, technology was developing from high-k metal gate planar FET to FinFET to MBCFET and now BSPDN.

FinFET, in the past known as a 3D transistor, was a key chip design technology during the development of 10nm foundry processes.

The gate surrounds the current channel in three sides which prevented the current leak.

But the recent move to single-digit nm processes meant FinFET was not enough.

Samsung introduced its gate-all-around, or GAA, technology that surrounds the current channel in four sides.

The company added what it called nanosheet instead of nanowire and calls the technology MBCFET.

BSPDN is different from this and should be understood as more of an evolution of the chiplet design used by Samsung, Intel and TSMC.

Instead of applying processes from a single company on a single chip, chiplet connects various chips from different companies made in different processes.

Also called 3D-SoC, it also combines logic with memory. Unlike the front side power delivery network, BSPDN utilizes the back side; the front side will have the logic functions and the back side used for power delivery or signal routing.

BSPDN as a concept was first introduced at IMEC in 2019. A paper on 2nm that cites the technology was also shown at IEDM in 2021.

The paper, in Korean called SRAM macro and the design and optimization of logic using the back end interconnection in 2nm process, claimed that BSPDN had 44% improved performance and 30% increased power efficiency compared to FSPDN.

The paper proposes that moving functions such as the power delivery network to the back of the chip can resolve the routing jam caused by using just the front side.


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