3D SoC with hybrid bonding applied was the way to overcome the current limitations of microfabrication the chip industry is facing, according to Inha University Professor Rino Choi.
And for application of hybrid bonding, back side power delivery network, and other advanced technologies, there need to be production technologies applied in the back end of chip production level to those in the front end, Choi said at a local chip conference hosted by TheElec on Wednesday.
Choi for semiconductor scaling, there needs to be innovation 3D SoC, not just 2D SoC.
Hybrid bonding and BPDN needed for this upgrade will require CMP, plasma processes, and cleanrooms at the back end.
Hybrid bonding bonds a heterogeneous chip die to the wafer. This can expand the I/O substantially compared to using solder balls.
At a space of 1 millimeter-square, between 10,000 to 100,000 vias can be connected, which are used for I/O or power delivery.
BPDN puts the power circuit on the back side of the wafer that improves cell use and prevents bottlenecks.
Hybrid bonding requires higher precision than conventional back end work and is more sensitive to defects.
TSMC is the only chip company that has commercialized hybrid bonding so far.
Called 3DFabric, the service has been applied to AMD V-Cache. Rivals Samsung and Intel are also preparing to offer similar services.
