Even in high bandwidth memory (HBM) hybrid bonding may be needed to pack in more layers within the confines of the package.
This is according to SK Hynix Wafer Bonding Head Kang Ji-ho, who said during a local chip conference hosted by TheElec that HBM with 12-layer or higher can face problems in height.
The chip giant already applies technologies such as through silicon via and mass reflow-molded underfill but this was not enough to check the chip’s size and direct bonding, also known as hybrid bonding, was needed for 12-layer HBM.
Hybrid bonding can remove the need for a filler bump that is used to connect the TSV with the HBM chip.
To apply hybrid bonding, application of chemical mechanical processing and other advanced processes will be needed to be applied in the back end of wafer fabrication, Kang noted.